Voltage regulation for up to 5 power transformers in parallel
Parallel transformer regulation by master-slave, circulating current and negative reactance methods.
It also includes line voltage drop compensation.
- Voltage Regulation. Maintains the transformer output voltage at the setpoint value, calculating the difference between the measured voltage and the setpoint voltage and comparing it with a threshold level to decide whether to send commands to the tap changer. The first tap change command has a time delay based on an inverse curve or a fixed time. Subsequent commands always have a fixed time delay.
- Line Voltage Drop Compensation. A compensation based on the measured current and the voltage drop between the transformer and the load, that provides stable voltage under load. The compensation can be calculated by two methods: LDC-Z or LDC-R & X.
- Parallel Transformers Regulation. Parallel transformer regulation can be achieved by the following methods:
- Master / slave
- Circulating current
- Negative reactance
The first two methods in the list allow voltage regulation for up to 5 parallel transformers using GOOSE messaging (IEC 61850 ed 1 and 2).
- Tap Indication and Monitoring. The active tap can be read by digital inputs (directly or in BCD code), by an analog current transducer or by a Resistor Chain. Tap monitoring permits to generate alarms corresponding to irregular or extreme tap positions and to failures after tap change commands.
- General characteristics of the “ZIV e-NET flex family”:
- Powerful programable logic
- 2000 event log. Up to 100 oscillography seconds
- Alphanumeric or graphic display
- Easy HW expansion without FW updates
- Unused protection elements can be hidden
- Custom mapping of physical current and voltage inputs to protection elements
- Can be used to protect multiple bays
- Up to 20 analog channels, 160 DI, 80 DO, and 22 LEDs
- Bonding, RSTP, PRP and HSR redundancy
- IEC 61850 ed. 1 & ed. 2 protocols, DNP3.0, Modbus RTU and PROCOME
- Native process bus. Analog input cards operate as Merging Units for the CPU. Synchronized samples at 4800 Hz (as per IEC 61869-9)
- Cybersecurity in accordance with IEC 62351 and IEEE 1686-2013 standards. RBAC, secure keys, physical and logical port disabling, cybersecurity event log, and securing of management protocols (PROCOME, HTTPS, SFTP, SSH)
- Time synchronization by IRIG-B, SNTP and PTP (Ordinary Clock / Transparent Clock)
- Data Sheet: H0RTFA1807Iv00